Digital Foundation IP development is not all about circuit and mask design. IP design in today’s latest nodes requires enormous cad validations which require push button flow and streamlined methodologies. We provide automatized design qualification methodologies which we also customize to customers' requirement basis. These automations are aimed at the following major domains.

  • Methodology Enhancement
    • Design Validation methodologies
    • Design Qualification methodologies
  • Characterization Flow
    • Circuit modeling and characterization
    • Timing and FE views generation
  • Library development Platform
    • Circuit Simulation environment
    • Characterization
    • Liberty and datasheet generation
    • Compiler GDS tiling
    • Compiler spice stitching
  • Quality Assurance